Brief introduction
More and more applications in the industrial, instrumentation, optical communication, and healthcare industries are adopting multi-channel data acquisition systems, leading to further challenges in terms of printed circuit board (PCB) density and thermal power consumption. The demand for high channel density in these applications has driven the development of integrated data acquisition solutions with high channel count, low power consumption, and small size. These applications also require precision measurement, reliability, economy, and portability. System designers make trade-offs between performance, thermal stability, and PCB density to maintain the best balance, and are forced to constantly seek innovative ways to address these challenges while reducing total material (BOM) costs. This article focuses on the design considerations of a multiplexed data acquisition system and addresses the technical challenges of space constrained applications such as optical transceivers, wearable medical devices, IoT, and other portable instruments by integrating multiplexed input ADC solutions. The low-power solution proposed in this article adopts an integrated multiplexing input of 4-channel/8-channel, 16 bit, 250 kSPS PulSAR ® ADCs AD7682/AD7689, It provides 2.39 mm × 2.39 mm small wafer level chip scale packaging (WLCSP), which can save more than 60% of board space and effectively solve the challenges of high channel density and battery powered portable systems, while also having flexible configuration and high-precision performance.
Multi channel data acquisition systems typically use different types of discrete single channel or integrated multiplexed and synchronously sampled analog signal chains to interface with various sensors, such as temperature, pressure, vibration sensors, and many other sensors based on application requirements. For example, multiplexing multiple input channels into one ADC, each channel using a sample and hold amplifier, and multiplexing multiple input channels into one ADC, each channel using one ADC for synchronous sampling. The first scenario usually uses a successive approximation type (SAR) analog-to-digital converter (ADC), as shown in Figure 1. It can save a considerable amount of power consumption, space, and cost, and the input of each channel may require a low-pass anti aliasing filter, whose channel switching and sequence are correctly synchronized with the ADC conversion time. The second scenario, as shown in Figure 2, requires the achievable throughput rate to be divided by the number of synchronously sampled channels, but the sampling channels can still maintain a constant phase. As shown in Figure 3, some applications require the use of dedicated amplifiers and ADCs for each channel and synchronous sampling of the input to improve the sampling rate of each channel and protect phase information, at the cost of increased board area and power consumption. Synchronous sampling ADC is commonly used in automatic testing equipment, power line monitoring, and multiphase motor control. These applications require each channel to continuously sample at a high throughput rate to protect the phase relationship between channels and achieve accurate instantaneous measurement.
Figure 1. Simplified multi-channel data acquisition signal chain - first scenario
Figure 2. Simplified multi-channel data acquisition signal chain - second scenario
Figure 3. Simplified multi-channel data acquisition signal chain - third scenarioThe key advantage of multiplexing is that each channel requires fewer ADCs, resulting in lower space, power consumption, and cost. However, the throughput rate achievable by a multiplexing system is equal to the throughput rate of a single ADC divided by the number of sampling channels. SAR type ADC has inherent advantages of low latency and dynamic power consumption proportional to throughput rate. They are commonly used in channel reuse architectures and are very suitable for detection and monitoring functions. The multiplexed data acquisition system used in the optical transceiver module requires high channel density, wearable medical devices require small size and low power consumption, signals from multiple sensors need to be monitored, and multiple input channels need to be multiplexed into a single or multiple ADCs. One of the main challenges of a multiplexed data acquisition system is that when the input switches to the next channel, it needs to quickly respond to step inputs approaching full range amplitude to minimize setup time or crosstalk issues. Below are practical examples of using SAR architecture based multiplexed input ADC for optical transceivers and wearable electronic devices, explaining why AD7689 is an ideal choice for such applications.
The 100 Gbps optical transceiver market will see growth opportunities in the next decade as it supports high-speed coherent optical transmission. The key challenge of optical transceivers is to collect and process signals with wider bandwidth, or to multiplex multiple input channels in a smaller space with lower power consumption. Today's transceivers were originally designed for remote applications, but their size, power consumption, and cost structure limit their use in cost sensitive metropolitan area networks. The metropolitan area network includes: 500 km to 1000 km in urban areas, 100 km to 500 km in urban cores, and 100 km or less in urban access applications. Due to fierce competition in metropolitan area networks and high spatial premiums, the density of line cards is extremely important. Therefore, low-cost optical line cards or smaller plug-in modules are becoming increasingly important for coherent applications.
In optical networks, as the bit rate of each channel increases from 10 Gbps to 100 Gbps or higher, non ideal factors in fiber optics can seriously degrade signal quality and affect its transmission performance. When fiber defects cause adverse effects such as optical noise, nonlinear effects, and dissipation, remote optical networks also face technical challenges. To address these major challenges, many 40 Gbps and 100 Gbps optical transceiver manufacturers use coherent technology to support higher data rate connections, maximum coverage, and longer distances to meet the demands of metropolitan remote, long-range, and ultra long range networks. Coherent technology generally integrates multi-level signal formats and coherent detection, using dual polarization, orthogonal and phase shift keying (DP-QPSK) to optimize signal modulation, thereby suppressing the fiber optic effects at higher data rates, making 100 Gbps transmission economically and technically feasible. The next generation of 100 Gbps (and above) data rate optical transceivers will require lower power consumption and smaller size to increase channel density, significantly saving space, power consumption, and costs. According to specific requirements, the number of channels in the optical system is usually between 8 and 64. For PCB designers, component placement and routing have become important, especially for high channel density systems.
Figure 4 shows a simplified block diagram of a universal optical module, which includes a transmitter, a receiver, a miniature ITLA (Integrated Tunable Laser Assembly), and a data acquisition device. Figure 5 shows a simplified block diagram of a miniature ITLA, which is a broadband electronically tuned laser device used for controlling fast wavelength switching. The transmitter includes a Mach Zehnder driver and modulator to control the amplitude or intensity of the emitted laser. Multi channel input ADCs are commonly used in control and monitoring functions to digitize data from multiple channels of optical modules and miniature ITLAs.
Figure 4. Simplified block diagram of optical module
Figure 5. Simplified Block Diagram of Micro Integrated Tunable Laser Components
Figure 6. Simplified block diagram of wearable electronic devices
Figure 7. Typical Application Block Diagram of AD7689 (Not All Connections and Decouplings Displayed)For multi-channel and multiplexing applications, some designers use low output impedance buffers to handle the kickback effects at the input of the multiplexer (depending on the throughput rate used). The input bandwidth of SAR ADC (tens of MHz) and ADC driver (tens to hundreds of MHz) is higher than the sampling frequency, and the required input signal bandwidth is usually in the range of tens of Hz to hundreds of kHz. Therefore, according to system requirements, the input of the multiplexer may require a single pole low-pass RC anti aliasing filter to eliminate unwanted signals (aliasing), prevent them from folding back into the target bandwidth, thereby limiting noise and reducing setup time issues. The RC filter values used for each input channel should be carefully selected based on the following trade-off relationship (as excessive band limiting may affect setup time and increase distortion): larger capacitors can help attenuate the kickback effects of the multiplexer, but may also reduce the phase margin of the previous amplifier stage, making it unstable. To ensure that the RC filter has high Q, low temperature coefficient, and stable electrical characteristics under varying voltages, it is recommended to use C0G or NP0 capacitors. Reasonable series resistance values should be selected to maintain amplifier stability and limit its output current. The resistance value should not be too high, otherwise the ADC driver will not be able to recharge the capacitor after the multiplexer backcharges.
Figure 8. Size comparison between AD7682/AD7689 wafer level chip scale packaging and standard pencilThe active side of the AD7682/AD7689 WLCSP chip is on the reverse side and can be connected to the PCB using solder balls. Figure 11 shows the chip size after PCB assembly. The actual distance (height from the board) between the chip surface and the substrate after PCB assembly is related to the solder mask and pad diameter printed on the substrate.
Figure 9. Dimensions of AD7682/AD7689 WLCSP after PCB assembly
Figure 10. Relationship between operating current and throughput rate of AD7682/7689
Figure 11. The relationship between SNR, SINAD, ENOB and reference voltage for AD7682/7689