Design of Front End Amplifier and RC Filter for Precision SAR Analog to Digital Converter

Sequential approximation (SAR) ADC provides high resolution, excellent accuracy, and low power consumption characteristics. Once a precision SAR ADC is selected, the system designer must determine the supporting circuits required to obtain high-quality results. The three main aspects to consider are: the front-end of the analog input signal and ADC interface, the reference voltage source, and the digital interface. This article will focus on the circuit requirements and trade-offs in front-end design. For useful information on other aspects, including specific device and system information, please refer to the data manual and references in this article

The front-end consists of two parts: a driver amplifier and an RC filter. The amplifier regulates the input signal while acting as a low impedance buffer between the signal source and the ADC input. RC filters limit out of band noise reaching the ADC input, helping to attenuate the kickback effect of switch capacitors in the ADC input.

Choosing the appropriate amplifier and RC filter for SAR ADC can be difficult, especially when applied for conventional purposes that differ from the ADC data manual. Based on various application factors that affect amplifier and RC selection, we provide design guidelines to achieve high-quality solutions. The main considerations include input frequency, throughput rate, and input reuse

Choose the appropriate RC filter

To choose a suitable RC filter, it is necessary to calculate the RC bandwidth for single channel or multiplex applications, and then select the values of R and C.

Figure 1 shows a typical amplifier, single pole RC filter, and ADC. The ADC input forms the switch capacitor load of the driving circuit. Its 10 MHz input bandwidth means that low noise needs to be ensured within the wide bandwidth to achieve good signal-to-noise ratio (SNR). The RC network limits the bandwidth of the input signal and reduces the amount of noise fed into the ADC by the amplifier and upstream circuit. However, excessive bandwidth restrictions can prolong the setup time and distort the input signal.Figure 1. Typical amplifier, RC filter, and ADC

The minimum RC value required for establishing ADC input and optimizing bandwidth to limit noise can be calculated by assuming that step inputs are established exponentially. To calculate the step size, it is necessary to know the input signal frequency, amplitude, and ADC conversion time. The conversion time, tCONV (Figure 2), refers to the time required for the capacitive DAC to disconnect from the input and perform bit judgments to generate digital codes. At the end of the conversion time, the capacitive DAC that saved the charge of the previous sample switches back to the input terminal. This step change represents the amount of change in the input signal during this period of time. The time required for establishing this step is called the 'reverse establishment time'

Figure 2. Typical timing diagram of an N-bit ADC

The maximum undistorted rate of change of a sine wave signal at a given input frequency can be calculated by the following equation:

If the conversion rate of the ADC greatly exceeds the maximum input frequency, the maximum change in input voltage during the conversion period is:

This is the maximum voltage step that occurs when the capacitive DAC switches back to the acquisition mode. Then, the parallel combination of DAC capacitor and external capacitor will attenuate this step. Therefore, the external capacitance must be relatively large, reaching several nF. This analysis assumes that the influence of input switch on resistance can be ignored. The step size that needs to be established now is:

Next, calculate the time constant for establishing the ADC input to half LSB during the ADC acquisition phase. Assuming that the step input is established exponentially, the required RC time constant τ is:

Among them, tACQ is the acquisition time, and NTC is the number of time constants required for establishment. The required number of time constants can be obtained by calculating the natural logarithm of the ratio of the step size VSTEP to the establishment error (in this case, half LSB):

Therefore,

Substituting the above formula into the previous one yields:

Equivalent RC bandwidth

Example: Using the RC bandwidth calculation formula, select the 16 bit ADCAD7980 (as shown in Figure 3) with a conversion time of 710 ns, a throughput rate of 1 MSPS, and a 5V reference voltage. The maximum target input frequency is 100 kHz. Calculate the maximum step at this frequency:

Then, the charge of the external capacitor will decay this step. Using a 27 pF DAC capacitor and assuming an external capacitance of 2.7 nF, the attenuation coefficient is approximately 101. Substitute these values into the VSTEP calculation formula:

Next, calculate the number of time constants established up to half LSB (16 bits, 5V reference voltage):

The collection time is：

Calculate τ：

Therefore, the bandwidth is 3.11 MHz and the REXT is 18.9 Ω

Figure 3. RC filter using 16 bit 1 MSPS ADC AD7980
The relationship between minimum bandwidth, throughput rate, and input frequency indicates that the higher the input frequency, the higher the required RC bandwidth. Similarly, the higher the throughput rate, the shorter the acquisition time, thereby increasing the RC bandwidth. The collection time has the greatest impact on the required bandwidth; If the collection time is doubled (reducing throughput rate), the required bandwidth will be halved. This simplified analysis does not include the second-order charge recoil effect, which becomes the main influencing factor at low frequencies. When the input frequency is very low (<10 kHz, including DC), a voltage step of approximately 100 mV is always established on the capacitive DAC. This value should be used as the minimum voltage step for the above analysis.

The multiplexed input signal is rarely continuous and usually consists of large steps generated by switching between different channels. In the worst case, one channel is at negative full-scale while the next channel is at positive full-scale (see Figure 4). In this case, when the multiplexer switches channels, the step size will be the full scale of the ADC, which is 5V for the above example.
Figure 4. Multiplexing Settings

When using multiplexed input in the above example, the filter bandwidth required for linear response will be increased to 3.93 MHz (with a step size of 5 V instead of 1.115 V for single channel). Assuming the following conditions: the multiplexer switches shortly after the start of the conversion (Figure 5), and the amplifier and RC have sufficient forward setup time to stabilize the input capacitor before the acquisition begins.

Figure 5. Multiplexing timing sequence

The calculated RC bandwidth can be checked using Table 1. From the table, it can be seen that in order to establish a full-scale step to 16 bits, 11 time constants are required (as shown in Table 1). For the calculated RC, the forward establishment time of the filter is 11 × 40.49 ns=445 ns, which is much shorter than the conversion time of 710 ns. The forward establishment does not need to occur entirely during the conversion period (before the capacitive DAC switches to the input), but the sum of the forward and reverse establishment times should not exceed the required throughput rate. For low-frequency inputs, the rate of signal change is much lower, so establishing a positive direction is not very important.

Table 1. Number of time constants required to establish to N-bit resolution

After calculating the approximate bandwidth of the filter, the values of REXT and CEXT can be selected separately. The above calculation assumes CEXT=2.7 nF, which is a typical value for the application circuit shown in the data manual. If a larger capacitor is chosen, the attenuation amplitude of the kickback will be greater when the capacitive DAC switches back to the input terminal. However, the larger the capacitance, the more likely the driver amplifier is to become unstable, especially when the REXT value is small under a given bandwidth. If the REXT value is too small, the amplifier phase margin will decrease, which may cause the amplifier output to oscillate or become unstable. For loads with small serial REXT, low output impedance amplifiers should be used to drive them. Stability analysis can be performed using the Bode plot of RC combination and amplifier to verify whether the phase margin is sufficient. It is best to choose a capacitance value of 1 nF to 3 nF and a reasonable resistance value to keep the driver amplifier stable. This requires the use of capacitors with low voltage coefficients, such as the NP0 type, to maintain low distortion.

The value of REXT must be able to maintain the distortion level within the required range. Figure 6 shows the effect of driver circuit resistance on distortion as a function of the input frequency of AD7690. Distortion increases with the increase of input frequency and source resistance. The main reason for this distortion is the nonlinear characteristics of the impedance provided by the capacitive DAC.
Figure 6. The relationship between the influence of source resistance on THD and input frequency
Low input frequency (<10 kHz) can support larger series resistance values. Distortion is also related to the amplitude of the input signal; For the same level of distortion, lower amplitudes can support higher resistance values. Calculate REXT in the above example, where τ=51.16 ns. Assuming CEXT is 2.7 nF, the resulting resistance value is 18.9 Ω. These values are close to the common values given in the application section of the ADI data manual.

The nominal RC value calculated here is a useful guide, but not the final solution. Choosing the appropriate balance point between REXT and CEXT requires understanding the input frequency range, the size of the capacitor that the amplifier can drive, and the acceptable level of distortion. In order to optimize the RC value, it is necessary to conduct experiments using actual hardware to achieve high-quality performance.

Choose the appropriate amplifier

In the previous section, we calculated the RC bandwidth suitable for ADC input based on the input signal and ADC throughput rate. Next, it is necessary to use this information to select a suitable ADC driver amplifier. The following aspects need to be considered:

Amplifier size signal bandwidth

Establishment time

Characteristics of amplifier noise and its impact on system noise

distortion

Distortion requirements for power rail margin

This data manual usually provides the small signal bandwidth of the amplifier. However, depending on the type of input signal, large signal bandwidth may be more important, especially for high input frequencies (>100 kHz) or multiplexing applications (due to large voltage swings), and the forward establishment of the input signal is more critical. For example, the small signal bandwidth of ADA4841-1 is 80 MHz (20 mV p-p signal), but the large signal bandwidth is only 3 MHz (2 V p-p signal). The above example uses AD7980, and the calculated RC bandwidth is 3.11 MHz. For lower input frequencies, ADA4841-1 is a good choice because its 80 MHz small signal bandwidth is more than sufficient for reverse establishment, but it is difficult in multiplexing applications because for large signal swings, the RC bandwidth requirement is increased to 3.93 MHz. In this case, a more suitable amplifier is ADA4897-1, which has a large signal bandwidth of 30 MHz. Generally speaking, the small/large signal bandwidth of an amplifier should be at least two to three times larger than the RC bandwidth, depending on whether it is primarily established in reverse or forward direction. If the amplifier stage is required to provide voltage gain (which reduces the available bandwidth), this principle is more applicable and may even require amplifiers with wider bandwidth.

Another way to view the requirement for positive establishment is to examine the establishment time characteristics of the amplifier, which typically refers to the time required to establish a certain percentage of the rated step size. For 16 bit to 18 bit performance, it is usually required to establish up to 0.001%, but most amplifiers only specify 0.1% or 0.01% establishment time for different step sizes. Therefore, in order to determine whether the established characteristics support ADC throughput rate, it is necessary to compromise these values. ADA4841-1 provides a 0.01% setup time of 1 μ s for an 8 V step. In the multiplexing application driving 1 MSPS (1 μ s cycle) AD7980, it will not be able to establish full-scale step inputs in a timely manner, but reducing throughput rates, such as 500 kSPS, may be feasible.

The RC bandwidth is crucial for determining the maximum allowable noise level of an amplifier. The amplifier noise is generally defined by the low-frequency 1/f noise (0.1 Hz to 10 Hz) and the broadband noise spectral density at high frequencies (the flat part of the noise curve shown in Figure 7).
Figure 7. Relationship between ADA4084-2 voltage noise and frequency

The total noise converted to the ADC input can be calculated as follows. Firstly, calculate the noise of the amplifier's broadband spectral density on the RC bandwidth.

Among them, en=noise spectral density (V/√ Hz), N=amplifier circuit noise gain, BWRC=RC bandwidth Hz

Then, the low-frequency 1/f noise is usually calculated using the following formula:; It is usually specified as peak to peak value and needs to be converted to root mean square value.

among，

=1/f peak to peak noise voltage, N=amplifier circuit noise gain.

The total noise is the sum root of the above two noises:

To minimize the impact of driver noise on the total SNR, this total noise should be around 1/10 of the ADC noise. According to the SNR requirements of the target system, higher noise may also be allowed. For example, if the SNR of the ADC is 91 dB and VREF=5 V, the total noise should be less than or equal to

It is easy to calculate the maximum allowable values for the spectral density of 1/f noise and broadband noise from this value. Assuming the proposed amplifier has negligible 1/f noise, operates at unity gain, and uses a filter with RC bandwidth as the calculated value (3.11 MHz), then

Therefore, the broadband noise spectral density of the amplifier must be less than or equal to 2.26 nV/√ Hz. The broadband noise spectral density of ADA4841-1 is 2.1 nV/√ Hz, which meets this requirement.

Another important characteristic that amplifiers need to consider is distortion at specific input frequencies. Typically, to achieve high-quality performance, a 16 bit ADC requires approximately 100 dB of total harmonic distortion (THD), while an 18 bit ADC requires approximately 110 dB. Figure 8 shows the typical distortion frequency relationship of ADA4841-1 for a 2 V p-p input signal.
Figure 8. Distortion and Frequency Relationship of ADA4841-1

The figure does not show total harmonic distortion, but rather the generally important second and third harmonic components. ADA4841-1 has very low noise and excellent distortion characteristics, sufficient to drive an 18 bit ADC to approximately 30 kHz. When the input frequency approaches 100 kHz or higher, the distortion performance begins to decrease. To achieve low distortion at high frequencies, it is necessary to use amplifiers with higher power consumption and wider bandwidth. Larger signals can also reduce performance. For ADC inputs ranging from 0 V to 5 V, the distortion performance signal range will be increased to 5 V p-p. From the distortion diagram shown in Figure 8, it can be seen that this will result in different performance, so the amplifier may need to be tested to ensure it meets the requirements. Figure 9 compares the distortion performance of multiple output voltage levels.

Figure 9. The relationship between distortion and frequency at different output voltage levels
Margin, which refers to the difference between the maximum actual input/output swing of the amplifier and the positive and negative rails, may also affect THD. An amplifier may have rail to rail inputs and/or outputs, or require a maximum margin of 1 V or even greater. Even for rail to rail input/output, if the operating signal level is close to the power supply rail of the amplifier, it will be difficult to achieve good distortion performance. Therefore, it is best to choose a power level that keeps the maximum input/output signal away from the power rail. Consider an ADC with an input range of 0 V to 5 V, driven by an ADA4841-1 amplifier, which requires maximizing the ADC's range. This amplifier has a rail to rail output with a margin requirement of 1 V for the input. If used as a unity gain amplifier, at least 1 V input margin is required, and the positive power supply must be at least 6 V. The output is rail to rail, but it can still only drive to ground or within approximately 25 mV of the positive power supply rail, so a negative power supply rail is needed to drive all the way to ground. To leave some margin for distortion performance, the negative power supply rail can be -1 V.

If it is allowed to reduce the input range of the ADC, thereby losing a certain SNR, the negative power supply can be eliminated. For example, if the input range of the ADC is reduced to 0.5 V to 5 V, this 10% loss will result in a decrease of approximately 1 dB in SNR. However, this can ground the negative power rail, eliminating the circuit used to generate negative power and reducing power consumption and costs.

Therefore, when selecting an amplifier, it is important to consider the requirements for the input and output signal ranges in order to determine the required power supply voltage. In this example, the amplifier with a rated operating voltage of 5 V cannot meet the requirements; But the rated voltage of ADA4841-1 is as high as 12V, so using a higher power supply voltage will achieve excellent performance and provide sufficient power margin.

Additional information about special components

Low power, low-noise, and low distortion operational amplifier with rail to rail output

ADA4841-1 low-power operational amplifier provides 2-nV/√ Hz broadband noise and -110 dBc spurious free dynamic range (SFDR), making it ideal for driving 16 bit and 18 bit PulSAR ® ADC， Suitable for portable instruments, industrial process control, and medical equipment. The characteristics of this unit gain stable amplifier include: 60 μ V input offset voltage, 114 dB open-loop gain, 114 dB common mode rejection, 80 MHz bandwidth (-3 dB), 12 V/µ s slew rate, and a 0.1% settling time of 175 ns. The input signal range can be extended to 100 mV below the negative power supply rail, and the output swing can reach within 100 mV of any power supply rail, providing single power supply operation capability. ADA4841-1 can be powered by a single power supply of 2.7 V to 12 V or a dual power supply of ± 1.5 V to ± 6 V. The power consumption in normal mode is 1.1 mA, and in power down mode it is 40 μ A. It is packaged in an 8-pin SOIC and has a rated temperature range of -40 ° C to+125 ° C. The quoted price for a thousand pieces is $1.59 per piece.

Low noise, low-power operational amplifier with rail to rail output

ADA4897-1 is a low-noise, high-speed operational amplifier with rail to rail output, 1 nV/√ Hz voltage noise, 2.8-pA/√ Hz current noise, 230 MHz bandwidth, 120 V/µ s slew rate, 45 ns setup time, and unity gain stability. It is an ideal choice for applications such as ultrasound, low-noise preamplifiers, driving high-performance ADCs, and buffering high-performance DACs. AD4897-1 is powered by a single power supply ranging from 3 V to 10 V, with a power consumption of 3 mA. It is packaged in 8-pin MSOP, LFCSP, and SOIC, with a rated temperature range of -40 ° C to+125 ° C, and a quote of $1.89 per thousand pieces.

16 bit, 1 MSPS successive approximation ADC with a power consumption of 7 mW

The AD7980 low-power successive approximation ADC provides 16 bit resolution, no code loss, and a sampling rate of 1 MSPS. It accepts pseudo differential inputs within the range of 0 to VREF, with characteristics including 91.5 dB signal-to-noise ratio (SINAD), -110 dB total harmonic distortion (THD), and maximum ± 1.25 LSB integral nonlinearity. The successive approximation architecture ensures no pipeline delay, while the daisy chain configuration allows multiple ADCs to share a bus. The gap between two conversions will automatically power off, and its power consumption is proportional to the throughput rate. The AD7980 is powered by a 2.5 V single power supply, with a power consumption of 7 mW at 1 MSPS, 70 μ W at 10 kSPS, and 350 pA in standby mode. It is packaged in a 10 pin MSOP and has a rated temperature range of -40 ° C to+85 ° C. The quoted price for a thousand pieces is $11.95 per piece.