Authors: Rick Downs and Miroslav Olaja from Texas Instruments

Operational amplifier output stage limit

The rail to rail operation of an operational amplifier refers to its input or output stage, or to its input and output stages. As a buffer driving the input of SAR ADC, we are more concerned with the rail to rail output capability of the operational amplifier. Generally speaking, this output capability indicates the degree to which the output stage can approach the power rail. This parameter can be found in most low-frequency or DC output signal product manuals, so a better understanding of the output swing capability will help determine the optimal operating point when driving the ADC input under established conditions.   

To determine the output stage limit, the following measurement work should be carried out in advance: for a rail to rail operational amplifier with a power supply voltage of 5V, the offset of the input signal is 2.5V or half of the power supply voltage. The operational amplifier should be set in advance in the voltage follower (or gain+1) configuration. The amplitude of the peak to peak input AC signal increased from 0 to 5V, reaching the power supply voltage level. When the output stage reaches its limit, it can display the measurement of total harmonic distortion and noise (THD+N) of different peak to peak output voltages at the output of the operational amplifier (see Figure 1).

Figure 1: Measured output signal of operational amplifier

Normally, when the signal amplitude increases, the low-frequency signal (1kHz) and total harmonic distortion remain unchanged. Only when the difference between the output voltage and the power rail is less than 10mV, will it cause a significant decrease in performance. As the frequency of the output signal increases, the difference between the output voltage and the power supply voltage also increases. For a 10kHz signal, the performance only begins to decline when the voltage difference is below 200mV; For a 20kHz signal, the performance only begins to decline when the voltage difference is below 300mV; and so on. If the correlation needs to remain unchanged, the swing of the output signal can be reduced as the frequency increases. For more information on the measurement results, please refer to Figure 2.

Figure 2: Measured operational amplifier distortion under different output signal conditions

Considering the output stage limit of the operational amplifier, these measurement results will help us determine the optimal operating point of the SAR ADC circuit. As in the above example, OPA365 with a power supply voltage of 5V can maintain its relevant performance unchanged even at a frequency of 150kHz and an output signal of up to 4.1VPP. Due to the 450mV margin left in the power rail, OPA365 can easily drive signals within the 100kHz range.

The impact of RC load on operational amplifiers

Previously, we have confirmed that for optimal AC performance, the output signal swing of an operational amplifier will be between 450mV and 4.55V. The second important parameter used to drive SAR ADC operational amplifiers is to identify their limits for driving different RC loads. Therefore, we strongly recommend using an RC filter at the input of the ADC to limit the bandwidth of input noise and help the operational amplifier drive the switched capacitor load generated by the SAR ADC. Figure 3 illustrates how the test setup circuit helps us determine the driving limit of an operational amplifier with RC load.

Figure 3: Measuring the Ability of Operational Amplifier to Drive RC Load

Firstly, set the cutoff frequency of the RC circuit to 1.5MHz. This frequency limit is set based on the expected acquisition time of the ADC to be used in future designs. In addition, if the cutoff frequency is to be kept constant, measurement work should be carried out for different RC combinations and different signal frequencies (please refer to Figure 4).

Figure 4: Distortion of operational amplifier measured under different RC conditions

For lower frequencies, we use resistors with smaller resistance values or capacitors with larger capacity. When the signal frequency increases, resistors with higher resistance should be used in conjunction with capacitors with smaller capacity to maintain stable performance. For OPA365 under established conditions, we found that improving performance by using resistors with a resistance of 50-100 Ω is not satisfactory - especially for higher signal frequencies, it is futile to improve performance by using resistors with a resistance of 50-100 Ω. For applied frequency, we can use resistors with a resistance greater than 100 Ω or capacitors with a capacity less than 1nF to maintain stable AC performance. When choosing the resistance value of resistors and the capacity of capacitors, we should follow the stability requirements of operational amplifiers.

Nonlinear characteristics of ADC input

Reducing the output voltage swing will help maintain the performance of the operational amplifier, but the integrity of the signal and its impact on different system components should also be considered. Subsequently, a signal can be sent to the input of the ADC. Figure 5 shows a common SAR ADC input stage. After passing through the input electrostatic discharge (ESD) protection diode, the signal in one sampling capacitor and two field-effect transistor (FET) switches can be sampled. If ideal components are used, this design will not have any impact on the driving of the operational amplifier during the sampling stage.

Figure 5: Input stage of SAR ADC

Unfortunately, these components are not ideal solutions (see Figure 6), especially the nonlinear characteristics of equivalent loads near the power rail, which pose new challenges to buffer circuits.

Figure 6: Equivalent load of SAR ADC operational amplifier

Reducing the signal swing from the operational amplifier to the ADC input will bring many benefits. Applying a 5VPP signal at the output of an operational amplifier will reduce total harmonic distortion (THD), especially at higher frequencies. In addition, when applying a 5VPP signal at the input of SAR ADC, it is required that the operational amplifier has strong driving capability, especially when it is close to the power supply voltage. Reducing the signal level from 5VPP to 4.1VPP with a 2.5V offset will increase the margin by 450mV for both positive and negative power rails. This setting makes it easier for operational amplifiers to provide satisfactory THD at higher frequencies. At present, the equivalent input load of ADC is in the linear region, making it easier for the operational amplifier to charge the sampling capacitor.

Another issue to consider is the full-scale attenuation of the ADC. In common ADC product manuals, it can be found that the rated power supply voltage of the converter is 5V, and its rated full range (FSR) is a 5VPP signal. Please note that the input FSR of the ADC depends on the application reference voltage, and you can adjust the FSR for new operating conditions. When the reference voltage used is 2.5V, for the Texas Instruments (TI) ADS8361, the FSR input signal will be ± 2.5V at 2.5V or 5VPP. After adjusting the reference voltage to 2.048V, the new (adjusted) FSR input signal will be ± 2.048V at 2.5V or 4.1VPP. Now, in the input signal of 4.1VPP, we have a full 16 bit conversion function without attenuating the dynamic range.

The relationship between collection time and throughput rate

When choosing an ADC, the most important parameters are speed or throughput. This parameter is a combination of acquisition (sampling) time and conversion time. The conversion time is the result of the combined effect of converter design and silicon processing technology used to achieve converter functionality. When the conversion time is shortened beyond the limit specified in the product manual, it will seriously affect the performance of the ADC. The conversion time usually varies depending on the maximum external clock used. In addition, according to the relevant instructions in the product manual, the best system design practice can keep the external clock within the limit or shorten the conversion time as much as possible. On the other hand, generally speaking, extending the conversion time does not improve the related performance.

The acquisition time is also clearly specified in the ADC product manual, which determines the speed of charging the sampling capacitor to achieve the specified throughput rate. As the collection time approaches its end, the input sampling switch is turned on, and the conversion process begins immediately. At the end of the conversion cycle, the data obtained from the ADC is equivalent to the voltage on the sampling capacitor at the beginning of the conversion cycle (or at the end of the acquisition cycle). Please refer to Figure 7.

No matter how excellent the ADC performance is, if there is not enough time to fully charge the sampling capacitor, the conversion result will not match the actual analog input signal. There are two methods to control the above parameters during system design: 1) using an operational amplifier with low output impedance and fast operating speed, or 2) using a high cutoff frequency RC filter at the ADC analog input. This method can lead to stability issues in operational amplifiers, while also causing significant noise impact on the input analog buffer circuit. Alternatively, you can extend the acquisition time of the converter by using operational amplifiers with moderate operating speeds and RC filters with lower cutoff frequencies.

Figure 7: ADC acquisition and conversion cycle

The throughput of ADS8361 is 500 kSPS, and the highest external clock frequency is 10MHz. The conversion process is divided into 16 clock cycles, which may take 1.6 µ s to complete. Only 0.4 µ s is used for simulating the input signal acquisition process. In a 16 bit system with a full scale of 5V, the ADC input sampling capacitor needs to be charged to reach the input signal level value with an error of less than 38 µ V. For driving operational amplifiers, this is a challenging task: adjusting the final value to less than 38 µ V within 400ns.

This problem can be alleviated by extending the collection time. For ADS8361, the specified conversion time is four times the acquisition time. If we extend the collection time by three times or 300%, we will be able to achieve 70% of the converter's maximum throughput, or 357 kSPS. Compared to the approach of obtaining related benefits by reducing the requirements for input signal buffer circuits, this sacrifice of speed is desirable. Table 1 shows the extension of ADS8361 acquisition time and corresponding decrease in throughput as a function of the number of external clock cycles.

Table 1: Throughput of a Collection Time Function

Optimize RC to achieve specific frequency performance

Now you can obtain the program for designing driver circuits. Firstly, choose an operational amplifier that is suitable for your system's power rail and record the input and output limits of this amplifier. At the same time, understand the possibility of adjusting the ADC input range to better match the performance of the operational amplifier. Secondly, determine the appropriate collection time and set the system timing accordingly. Next, select the relevant values in the RC circuit, and the ratio (k) between the acquisition time and the RC filter time constant depends on the resolution of the ADC. Finally, select an operational amplifier with sufficient gain bandwidth to drive the RC circuit, and the selected operational amplifier should have appropriate adjustment time. For many applications of different SAR converters, the program for designing the driver circuit is very robust and effective. However, sometimes as optimization measures for RC filters that can improve performance systems, this is just the beginning.

For example, we plan to optimize the circuit we previously discussed. Before exploring how to optimize the input RC filter of ADS8361 front-end, we need to determine the relevant working conditions: the input clock frequency used is 9.9968MHz, and the set sampling frequency is 199.936kSPS; The result generated by these two values is that the conversion time of the ADC is 1.6 µ s, while the sampling time is 3.4 µ s. Therefore, for this 16 bit converter, we need an external RC filter with 12 time constants to match the corresponding acquisition time. This condition can set the bandwidth of the RC circuit to:

It is: k=12, which can achieve a bandwidth of 562kHz.

For a low-noise system, the highest possible bandwidth can be used according to actual needs. However, do not set the bandwidth too high. Because the higher the bandwidth, the higher the allowed noise, it is necessary to strike a balance between the RC setting time and the bandwidth.

To determine the optimal value of the RC filter, we used a signal source with low output impedance. Figure 8 shows the test setup used for measurement.

Figure 8: Selecting an RC filter by using an ideal signal source

With this setting, the measurement results will not be affected by the input buffer. It is worth noting that the final calculation result should include the output impedance of the signal source. In the example described, the impedance is 20 Ω. Please refer to Figure 9-10 for measurement results.

Figure 9: THD values measured at different RC constants

Figure 10: SNR, SFDR, and SINAD values measured at different RC constants

From these measurement results, we found that the optimal THD value can be obtained when k=7; When k=6, the optimal SFDR value can be obtained. And it can also be intuitively seen that these measurement results have a certain significance: because the smaller the k value, the lower the bandwidth of the RC filter, thereby reducing noise. However, as the value of k decreases, we find that performance also decreases. This situation occurs because the time constant is too large, and it cannot adjust the input voltage on the sampling capacitor accordingly, resulting in measurement errors.

In addition, we also found from the measurement results that the performance difference between the designed procedure and the optimal value is about 2-3 dB. Depending on the specific application situation, this difference may or may not be significant. Why is there a discrepancy between program design and optimal results? Because the design program assumes that the worst-case scenario occurs when charging the ADC input sampling capacitor. Therefore, the most conservative value was set for adjusting the time; Through testing to optimize performance, we often find that the operating conditions of the circuit are not the worst, and we also discover that some assumptions used to determine the design program must be corrected.

Conclusion

To complete the final performance evaluation of the signal chain, we selected an RC filter with k=6.36 or cutoff frequency=298kHz. Under this premise, we use a 2.2nF COG capacitor and a 243 Ω resistor. Extending the acquisition time to reduce the operating speed of the ADC has other advantages: the cut-off frequency of the filter limits the effective noise bandwidth of the ADC input signal and the operational amplifier output signal.

When using the highest sampling speed of ADC, the acquisition time is 400ns. When using the same standard as above (k=6.36), the effective noise bandwidth of the first-order filter is 4MHz.

When the acquisition time is extended from 400ns to 3.4 µ s, the effective noise bandwidth decreases to 562kHz.

When selecting configurations and component values, please use the results obtained from the above measurements. Figure 11 shows the final adjustment chart.

Figure 11: Final measurement adjustment

By comparing the measurement results, we found that this program is so important when designing the signal chain. As a reference, we used the values in the ADS8361 product manual. Next, we will compare the results obtained from the test with the RC filter selected for the ADC front-end. From Table 2, we can see that there is a decrease in THD performance, which can be attributed to the signal source (obviously, this is not the same signal source used to describe the characteristics of ADS8361). Finally, the measurement results obtained from the overall solution need to be compared. This solution includes OPA365 with RC filter and ADS8361.

Table 2 Comparison of Final Measurement Results

At this point, you can conclude that a reasonable design of the buffer circuit at the front end of the ADC converter will not reduce the performance of the system. Figure 12 shows the FFT measurement results of the entire system.

Figure 12: Measurement results of the entire signal chain

Inference

We introduced the design program of SAR type ADC driver circuit, which focuses on the requirements of operational amplifiers and several technologies for optimizing operational amplifiers and ADC systems. At the same time, we also explained how to further optimize the RC circuit of the SAR front-end, but these performance adjustments vary for different applications, so careful consideration is needed. In addition, we also found that a reasonable design of the buffer circuit at the front end of the ADC converter does not reduce the performance of the system.

About the author

Rick Downs graduated from the University of Arizona with a Bachelor of Science in Electronic Engineering (BSEE) degree and currently serves as the Application Engineering Manager for TI Data Acquisition Products. Currently holds 4 patents.

Miroslav Olajaca graduated from the Electrotechnical University in Belgrade, Yugoslavia, with a Bachelor of Science in Electronic Engineering (BSEE) and a Master of Science in Electronic Engineering (MSEE). She is currently a System Engineer for TI Data Acquisition Products.