Where is BCD technology heading?

2024-10-31

Source: Content from Semiconductor Industry Observation (ID: icbank) Comprehensive, thank you.

According to YOLE, BCD technology is mainly aimed at simplifying the control of power devices in the automotive, industrial, and consumer fields. It combines three types of transistors on the same chip: bipolar transistors for analog functions, CMOS (complementary metal oxide semiconductor) for digital functions, and DMOS (double diffusion MOS) for power functions and high voltage regulation.

Data shows that the revolutionary BCD technology was invented by ST in the mid-1980s and has been continuously developed since then. This three in one integration has significant advantages, as it can reduce PCB footprint, chip area, and electromagnetic interference. With the help of new BCD technology, manufacturers aim to add improved power characteristics for high-density digital and analog functions. This requires thicker gate oxide layers and more complex isolation techniques.

In 2021, IEEE also awarded ST the "IEEE Milestone for Multiple Silicon Technologies on a Chip" for this technology.

Amazing BCD technology

According to IEEE reports, after the introduction of ICs in the 1950s, several variants of this technology emerged: technology based on bipolar transistors invented in the 1950s; CMOS in the 1960s; And the double diffusion metal oxide semiconductor (DMOS) from the 1970s. But in the early 1980s, some applications required all three types of chips, namely chips with higher voltage and faster switching speed.

With the development of technology, chips are under increasing pressure. According to an entry in the Engineering Technology History Wikipedia, the switching mode of devices is limited by the low efficiency of chips. The amount of electricity delivered to electronic devices is also hindered.

At that time, SGS (now STMicro Electronics) realized that the functionality of its bipolar transistors and CMOS and DMOS chips was insufficient to run certain applications. Bruno Murari, an IEEE member who leads the BCD transistor research team, said that we need something more robust.

To this end, a research team was established in the early 1980s, dedicated to exploring how to combine bipolar, CMOS, and DMOS technologies. This includes chip experts Antonio Andreini, Claudio Contiero, and Paola Galbiati.

Murari said that the team is focused on customer needs: "Our goal is to provide power in the range of hundreds of watts under the control of digital logic, which can be expanded according to Moore's Law." The developed chip will also support precise simulation functions and minimize power consumption to eliminate heat sinks.

Murari visited customers to better understand what chip features they need. He stated that it is clear that they want the power and performance of DMOS, as well as the control logic, accuracy, and low noise provided by CMOS and bipolar transistors. By combining chip technology, the company will be able to integrate heterogeneous transistors and diodes on a single chip.

The team knows what the requirements are, but has encountered difficulties in providing them.

The answer came when Murari discovered that researchers at the company's Castellaneta factory had developed a DMOS transistor with a V-shaped logic gate (a small transistor component). Murari realized that this design could overcome the existing power limitations of bipolar transistors and use it as the basis for BCD chips.

Although the goal of integrating bipolar transistors, CMOS, and DMOS on a single chip is difficult, this work is very exciting, "Murari said. Everyone is dedicated to this project

The company launched its first BCD super integrated circuit, the L6202 full bridge motor driver, in 1985. Its operating voltage is 60 volts, current is 1.5 amperes, and switching power is 300 kHz.

ST CEO Jean Marc Chery stated that as of 2021, STMicroelectronics has produced 9th generation BCD chips and 5 million wafers, and has sold 40 billion BCD chips.

And this Milestone plaque will be displayed at ST Milan headquarters. The plaque reads:

SGS (now STMicroelectronics) was the first to introduce the ultra integrated silicon gate process, combining bipolar, CMOS, and DMOS (BCD) transistors on a single chip, suitable for complex, high-power applications. The first BCD super integrated circuit is called L6202, which can control up to 60V-5A current at 300 kHz. Subsequently, this process technology was widely adopted in automobiles, computers, and industrial applications, enabling chip designers to flexibly and reliably combine power, analog, and digital signal processing.

Smaller nodes become the development direction

Yole further pointed out that with higher voltage breakthroughs and the goal of transistor density, traditional local oxidation of silicon (LOCOS) isolation technology has been largely replaced by more advanced technologies since 2008. Shallow trench isolation (STI) is used in CMOS transistors to create active structures with smaller and tighter isolation, which helps improve device packaging levels and overall better circuit performance and reliability. For high-voltage functions, the etching depth used in STI is not sufficient to effectively surround charged particles. In this case, deep trench isolation (DTI) is preferred.

However, this method involves two additional masks and cannot be used to create gate oxides for lateral DMOS transistors. In such components, the results provided by STI are not as good as those obtained using the LOCOS method, which still has correlation without the need for high voltage. In order to achieve more functionality and smaller technological nodes, BCD technology now typically includes a combination of two technologies (STI/DTI, LOCOS/DTI), and in some cases even three technologies (LOCOS, STI, and DTI), making the manufacturing process simpler. Even more complex.

In addition, silicon on insulator (SOI) substrates ensure perfect isolation between different transistors and are an essential solution for high-voltage devices.

Yole further pointed out that as the complexity of larger digital functions shrinks to smaller chips, more metal layers need to be integrated to ensure the interconnection of CMOS transistors. Commonly seen in aluminum (NXP 0.14 µ m BCD technology, six layers), copper layer integration (Infineon SPT9 0.13 µ m BCD technology, five layers of copper, or Intel PMB6829 0.065 µ m BCD technology, six layers of copper), and one layer of aluminum). Due to its inherent properties, copper can reduce gate delay in digital functions, improve electromigration durability, and enhance thermal management.

The new BCD technology also features MIM (Metal Insulator Metal) capacitors, which can be stacked onto any metal layer serving as the first electrode. This architecture allows for the addition of more features without any impact on the chip area.

The integration of advanced isolation technology, additional metal layers, and MIM capacitors means more complex manufacturing processes and requires specific equipment. From the previous generation with less than 20 masks, to the current new generation, the manufacturing process requires an average of over 35 masks. Therefore, the cost of wafers increases with the reduction of technology nodes, especially when using SOI substrates (much more expensive than other substrates) or copper layers, which require dedicated clean room environments.

The cost of a wafer also depends on its size. The smallest technological node (less than 0.09 μ m) requires expensive production equipment and is only suitable for 300mm wafer fabs. However, these new technologies allow for the installation of more BCD chips on each wafer, and in some cases, can balance the additional costs incurred due to more complex manufacturing processes, specific equipment, and additional raw materials.

Nowadays, very advanced technology nodes (<0.09 μ m) are still quite unique. But major manufacturers such as Infineon Technologies, STMicroelectronics, and Intel, which fully develop and manufacture BCD chips, have already invested in 300mm wafer fabs to predict future demand in the field and increase production capacity.

For example, in the field of Lianhua Electronics, the company's BCD technology nodes range from 0.5um to 110nm. The device products include LV MOS, HV DMOS, mixed signal and analog devices, passive devices, and embedded non-volatile memory, covering consumer, computing, communication, industrial, and automotive industries.

TSMC was the first foundry to use 300mm wafers to produce BCD power management technology.

According to TSMC, the company's BCD power management process has higher integration, smaller footprint, and lower power consumption, covering nodes from 0.6 μ m to 40nm. The customer chips produced through this process can provide more stable and efficient power supply, consume less energy, and are very suitable for applications such as consumer electronics, communication equipment, and computers.

TSMC's 12 inch 0.13 μ m BCD Plus technology has excellent cost competitiveness compared to the previous 0.13 μ m BCD technology, has passed customer process validation, and began production in the second half of 2017.

The third-generation 0.18 μ m BCD began mass production in the second half of 2017 and obtained AEC-Q100 Level 1 qualification in 2018. Compared with the second-generation BCD, this technology has excellent cost competitiveness.

TSMC's 8-inch 90 nanometer BCD technology is expected to pass qualification certification and is currently undergoing customer wafer fabrication. Compared with the 0.18 μ m BCD platform, this technology provides excellent cost competitiveness, especially in the power management IC platform of 5G smartphones.

TSMC's integrated RRAM model's 12 inch 40 nanometer BCD technology is expected to be certified in August 2019. This technology provides functionality for high-speed communication interfaces such as smartphones and the Internet of Things.

Some other companies that have not invested in new generation factories have already developed fabless or wafer fab models, either partially developed, such as ADI, which outsources BCD chip manufacturing for technology nodes smaller than 0.18 μ m to TSMC, or fully developed, such as ADI. Melexis collaborates with X-Fab and SMIC respectively.